A framework for GPU-accelerated AES-XTS encryption in mobile devices

Attacks on data stored in mobile devices are increasingly getting more efficient and successful, especially with the use of advanced cryptanalysis techniques and high-tech systems. Encryption using the IEEE XTS-AES algorithm might be an attractive solution for this problem, but it comes with a significant impact on the performance of these limited-resources devices. The emergence of the potential Graphical Processing Units (GPUs), as a general purpose non-graphical computational power, has gained a great interest in both industry and academia. Recently, GPUs have presented higher performance for parallel programming than conventional CPUs while they continue gaining reduced cost. One important application area that can benefit from GPUs power is storage encryption in mobile devices. In this paper, we introduce a GPU-accelerated framework for storage encryption in mobile devices using the XTS-AES encryption algorithm. The Google's Android is targeted in this work as a mobile operating system

Impact of intrinsic parameter fluctuations in ultra-thin body silicon-on-insulator MOSFET on 6-transistor SRAM cell

As CMOS device dimensions are being aggressively scaled, the device characteristic must be assessed against fundamental physical limits. Nanoscale device modelling and statistical circuit analysis is needed to provide designer with ability to explore innovative new MOSFET devices as well as understanding the limits of the scaling process. This work introduces a systematic simulation methodology to investigate the impact of intrinsic parameter fluctuation for a novel Ultra-Thin-Body (UTB) Silicon-on-Insulator (SOI) transistor on the corresponding device and circuits. It provides essential link between physical device-level numerical simulation and circuit-level simulation. A systematic analysis of the effects of random discrete dopants, body thickness variations and line edge roughness on a well scaled 10 nm, 7.5 nm and 5 nm channel length UTB-SOI MOSFET is performed. To fully realise the performance benefits of UTB-SOI based SRAM cells a statistical circuit simulation methodology which can fully capture intrinsic parameter fluctuations information into the compact model is developed. The impact of intrinsic parameter fluctuations on the stability and performance of 6T SRAM has been investigated. A comparison with the behaviour of a 6T SRAM based on a conventional 35 nm MOSFET is also presented

Development of a miniature robot for swarm robotic application

Biological swarm is a fascinating behavior of nature that has been successfully applied to solve human problem especially for robotics application. The high economical cost and large area required to execute swarm robotics scenarios does not permit experimentation with real robot. Model and simulation of the mass number of these robots are extremely complex and often inaccurate. This paper describes the design decision and presents the development of an autonomous miniature mobile-robot (AMiR) for swarm robotics research and education. The large number of robot in these systems allows designing an individual AMiR unit with simple perception and mobile abilities. Hence a large number of robots can be easily and economically feasible to be replicated. AMiR has been designed as a complete platform with supporting software development tools for robotics education and researches in the Department of Computer and Communication Systems Engineering, UPM. The experimental results demonstrate the feasibility of using this robot to implement swarm robotic applications

Dynamic process migration framework

Process migration refers to the act of transferring a process in the middle of its execution in a network. The majority of today's computing power exists in the form of workstations. Increasing use of autonomous workstations connected by a high-speed network represents substantial opportunity for sharing more resources and designing a highly available system much cheaper than a high performance single machine. The process migration framework as a bare facility should be included in all Operating Systems (OSs). In this paper, we describe the design and implementation of process migration framework for Linux OS which aims to segregate the process migration mechanism from the system design and provide the capability of dynamically extending the process migration system on demand to increase compatibility and reduce the system overhead

Optimizing of ANFIS for estimating INS error during GPS outages.

Global positioning system (GPS) has been extensively used for land vehicle navigation systems. However, GPS is incapable of providing permanent and reliable navigation solutions in the presence of signal evaporation or blockage. On the other hand, navigation systems, in particular, inertial navigation systems (INSs), have become important components in different military and civil applications due to the recent advent of micro-electro-mechanical systems (MEMS). Both INS and GPS systems are often paired together to provide a reliable navigation solution by integrating the long-term GPS accuracy with the short-term INS accuracy. This article presents an alternative method to integrate GPS and INS systems and provide a robust navigation solution. This alternative approach to Kalman filtering (KF) utilizes artificial intelligence based on adaptive neuro-fuzzy inference system (ANFIS) to fuse data from both systems and estimate position and velocity errors. The KF is usually criticized for working only under predefined models and for its observability problem of hidden state variables, sensor error models, immunity to noise, sensor dependency, and linearization dependency. The training and updating of ANFIS parameters is one of the main problems. Therefore, the challenges encountered implementing an ANFIS module in real time have been overcome using particle swarm optimization (PSO) to optimize the ANFIS learning parameters since PSO involves less complexity and has fast convergence. The proposed alternative method uses GPS with INS data and PSO to update the intelligent PANFIS navigator using GPS/INS error as a fitness function to be minimized. Three methods of optimization have been tested and compared to estimate the INS error. Finally, the performance of the proposed alternative method has been examined using real field test data of MEMS grade INS integrated with GPS for different GPS outage periods. The results obtained outperform KF, particularly during long GPS signal blockage

A framework for system dependability validation under the influence of intrinsic parameters fluctuation

This paper presents a framework to analyze and evaluate effects of cell failures induced by impact of intrinsic parameters fluctuation (IPF) on system dependability. The method of evaluation is based on generating the actual cell failures model and the realistic conditions of hardware-software interactions, where the actual error pattern can be captured. The case study of this paper is the impact of cell failures in L1 data cache of a general-purpose microprocessor. The failure modules are generated corresponding to the individual and combined impact of IPF sources in nanometer scale Ultra Thin Body – Silicon on Isolator (UTB-SOI) transistor on 6T-SRAM cell stability. A novel fault injection mechanism has been introduced to propagate errors, through modifying data of cache transactions according to error(s) incurred, dynamically at system-level. By applying a representative system workload using a well-selected suit of real benchmark programs, this study demonstrates that the framework: 1) provides an accurate user visible description for the implications of cell failures at the higher levels of abstraction induced by IPF sources at the lower levels of abstraction, 2) links individual and combined impact of IPF sources with the corresponding implications at system-level which offers a tool to systems designer to involve IPF impacts within the design plan, 3) allows for a detailed simulation process of a system-level environment in the presence of cell failures induced by IPF within an accepted period of time using the look-up file technique and thus offers a foundation to system dependability studies that require vast statistical models, 4) offers high credible evaluation results because the framework is based on the actual error pattern incurred in the system, and 5) improves system reliability where it offers valuable perceptions for an optimal fault tolerance technique in L1 cache with a high failures rate

Unsupervised place recognition for assistive mobile robots based on local feature descriptions.

Place recognition is an important perceptual robotic problem, especially in the navigation process. Previous place-recognition approaches have been used for solving ‘global localization’ and ‘kidnapped robot’ problems. Such approaches are usually performed in a supervised mode. In this paper, a robust appearance-based unsupervised place clustering and recognition algorithm is introduced. This method fuses several image features using speed up robust features (SURF) by agglomerating them into a union form of features inside each place cluster. The number of place clusters can be extracted by investigating the SURF-based scene similarity diagram between adjacent images. During a human-guided learning step, the robot captures visual information acquired by an embedded camera and converts them into topological place clusters. Experimental results show the robustness, accuracy, and efficiency of the method, as well as its ability to create topological place clusters for solving global localization and kidnapped robot problems. The performance of the developed system is remarkable in terms of time, clustering error, and recognition precision

A parallel XTS encryption mode of operation

Securing data stored inside the storage devices is becoming an important concern in computer security now. It is known that the most efficient techniques to protect storage devices are using cryptography. Developing newer and more secure encryption algorithms and modes of operation might be critically important to protect these devices since conventional disk encryption algorithms, such as CBC mode, have shown serious security flaws. In this paper, the newly standardized IEEE XTS encryption mode of operation for storage encryption (P1619 standard) has been implemented using parallel design. A performance comparison between the sequential and parallel algorithms of XTS mode has been presented. The parallel XTS algorithm has shown a speedup of 1.80 (with 90% efficiency) faster than the sequential algorithm. In these simulations, AES is used as encryption algorithm with 256-bit encryption key

File integrity monitor scheduling based on file security level classification

Integrity of operating system components must be carefully handled in order to optimize the system security. Attackers always attempt to alter or modify these related components to achieve their goals. System files are common targets by the attackers. File integrity monitoring tools are widely used to detect any malicious modification to these critical files. Two methods, off-line and on-line file integrity monitoring have their own disadvantages. This paper proposes an enhancement to the scheduling algorithm of the current file integrity monitoring approach by combining the off-line and on-line monitoring approach with dynamic inspection scheduling by performing file classification technique. Files are divided based on their security level group and integrity monitoring schedule is defined based on related groups. The initial testing result shows that our system is effective in on-line detection of file modification

Fast cellular automata implementation on graphic processor unit (GPU) for salt and pepper noise removal

Noise removal operation is commonly applied as pre-processing step before subsequent image processing tasks due to the occurrence of noise during acquisition or transmission process. A common problem in imaging systems by using CMOS or CCD sensors is appearance of the salt and pepper noise. This paper presents Cellular Automata (CA) framework for noise removal of distorted image by the salt and pepper noise. In order to enhance the performance of the designed CA for noise removal, a parallel programming approach has been adopted and implemented on GPU. The results obtained show that the proposed CA models implemented on general purpose processor and GPU are able to suppress noise in high noise intensity up to 90 percents. The proposed CA implemented on GPU has successfully outperformed the method implemented on CPU by factor of 2 for gray scale image and factor of 10 for color images